| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a micro processor capable of performing a task execution and an intermittent DMA transfer simultaneously and terminating the execution of a task operating in a processor core part by a dead line. SOLUTION: A DMA transfer determination part 8 outputs DMA transfer rate correction information to a DMA controller part 4 by using, as input information, the start time information on execution task, dead line time information, and calculation time information sent from the processor core part 2, and DMA transfer rate information sent from a DMA transfer rate storage part 7. By lowering an intermittent DMA transfer amount during task execution, the task execution can be terminated by the dead line.</p> |
