| 摘要 |
The present invention provides a method for improving the planarization of a top layer deposited over a patterned layer on a semiconductor wafer. The patterned layer may include both small and large features. Openings, grooves, or trenches are etched partially or completely through certain larger target features in the patterned layer in an effort to mimic the topography of areas where the patterned layer includes smaller features. Subsequent deposition of the top layer may result in a more consistent or regular topography across the surface of the top layer. Accordingly, high areas on the top layer that contact a polishing pad of a CMP system will tend to be removed at a similar rate since the pressure exerted by each of the high areas will be similar. |
