发明名称 DATA PROCESSOR
摘要 A data processor in which a CPU performs predetermined processings while accessing an external memory such as an SDRAM. The processing capacity of a system constructed by the data processor is maintained, or improved while considerably reducing the power consumption of the system. The data processor comprises CPU 21 for performing a predetermined processing while accessing an external SDRAM 31 and an SDRAM controller 24 for control the access to the SDRAM 31 in response to a request of the CPU 21. The operating clock Φ1 of the CPU 21 is set to a relatively low speed, and the operating clock Φ2 of the SDRAM controller 24 is set to a relatively high speed.
申请公布号 WO03032168(A1) 申请公布日期 2003.04.17
申请号 WO2002JP02698 申请日期 2002.03.20
申请人 SUPREME MAGIC CORPORATION;KOBAYASHI, TSUKASA 发明人 KOBAYASHI, TSUKASA
分类号 G06F12/00;G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F12/00
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