DESKEWING GLOBAL CLOCK SKEW USING LOCALIZED ADJUSTABLE DELAY CIRCUITS

摘要

A method for reducing global clock skew by referencing a first point on an integrated circuit to which to align other points on the integrated circuit is provided. Further, an integrated circuit that has localized adjustable delay circuits having adjustable buffers that selectively drive a signal on a clock grid is provided. Further, a technique for using a local DLL, one or more phase detectors, and one or more adjustable delay circuits connected to portions of a clock grid to reduce clock skew is provided.