| 摘要 |
A machine or method used in signal processing transforms involving computation of one or more sums each of one or more products. A first multiplier computes a first product and a first set of intermediate terms. A second multiplier computes a second product using one or more of the terms computed by the first multiplier. Because they share computations, the two multipliers can have lower implementation cost than if they function separately. The invention is particularly useful in signal processing transforms that have fixed weights, such as discrete Fourier transforms, discrete cosine transforms, and pulse-shaping filters. These transforms are multiply-intensive and are used repeatedly in many applications. Implementations of shared multiplication techniques can have reduced chip space, computation time, and power consumption relative to implementations that do not share computation. Depending on the properties of the transform being computed, shared multiplication can exploit constant numbers, variable numbers from limited sets of allowed values, and restrictions on one or both numbers in particular products.
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