发明名称 Apparatus for measuring parasitic capacitances on an integrated circuit
摘要 The novel apparatus permits precise measurements of parasitic capacitances. The apparatus has a test structure and a reference structure, each with two conductor tracks. In the reference structure, the two conductor tracks are always at the same potential. In the test structure, one conductor track is coupled to ground potential and the other conductor track to a different potential. The test structure and the reference structure are connected to a voltage potential and the charge which builds up on the test structure and the reference structure is registered. The parasitic capacitance can be calculated precisely from the charge difference. The conductors of the test structure and of the reference structure are arranged in such a way that each conductor perceives a relationship to capacitive parasitic effects in the same environment.
申请公布号 US2003071641(A1) 申请公布日期 2003.04.17
申请号 US20020234079 申请日期 2002.09.03
申请人 ARMBRUSTER HANS-ULRICH 发明人 ARMBRUSTER HANS-ULRICH
分类号 G01R31/28;(IPC1-7):G01R27/26 主分类号 G01R31/28
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