Programmable feedback delay phase-locked loop for high-speed input/output timing budget management and method of operation thereof

摘要

A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.