发明名称 Semiconductor device having dummy patterns for metal CMP
摘要 A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 mum. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.
申请公布号 US2003071263(A1) 申请公布日期 2003.04.17
申请号 US20020309272 申请日期 2002.12.04
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 KOUNO HIROYUKI;KUMAMOTO TOSHIO;MIKI TAKAHIRO;SATOH HISAYASU
分类号 H01L23/52;H01L21/3105;H01L21/3205;H01L21/768;H01L21/82;H01L21/822;H01L21/8234;H01L23/522;H01L23/528;H01L27/04;H01L27/08;H01L29/423;H01L29/78;(IPC1-7):H01L23/58 主分类号 H01L23/52
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