发明名称 |
A microprocessor having a multiply operation |
摘要 |
A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location. <IMAGE>
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申请公布号 |
EP1302848(A2) |
申请公布日期 |
2003.04.16 |
申请号 |
EP20020028954 |
申请日期 |
1995.12.01 |
申请人 |
INTEL CORPORATION |
发明人 |
PELEG, ALEXANDER;YAARI, YAAKOV;MITTAL, MILLIND;MENNEMEIER, LARRY M.;EITAN, BENNY |
分类号 |
G06F9/305;G06F5/00;G06F7/52;G06F9/30;G06F9/302;G06F9/38;(IPC1-7):G06F9/302 |
主分类号 |
G06F9/305 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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