| 摘要 |
The digital filter (FLT) receives an input signal (INPUT(G)) including possible voltage peaks or glitches from a square-wave clock signal generator (CLK), and comprises a delay line (T) producing a delayed digital signal (INPUT(G)+ delta t), the positive front detector (PF) and the negative front detector (NF) producing the positive front and the negative front indicator signals (P,N) on the basis of the delayed digital signal, two mixers (M1,M2) producing the positive front and the negative front filtering indicator signals (P',N') on the basis of the input digital signal (INPUT(G)) and the indicator signals (P,N), and a third mixer (M3) producing an output signal (OUTPUT) without voltage peaks on the basis of the filtering indicator signals (P',N'). <??>The time delay ( delta t) of the delayed digital signal relative to the input digital signal is at least equal to the maximum length of the voltage peak or glitch (G). The first mixer (M1) has the function of logic AND, and the second mixer (M2) has the function of set inverter of logic AND. The third mixer (M3) is an RS-type bistable. The positive front and the negative front detectors (PF,NF) are D-type bistables with inverter branches each connecting a Q output to a reset input (R). A method for filtering an input digital signal including a voltage peak or a glitch is claimed and implemented by the device. A real-time clock module (RTC) comprises a square-wave clock signal generator (CLK) and a digital filter (FILT) as proposed. A portable telephone comprises the real-time clock module. |
