Array VT mode implementation for a simultaneous operation flash memory device

摘要

An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.