| 发明名称 |
Variable delay circuit and semiconductor integrated circuit device |
| 摘要 |
A variable delay circuit includes a load on a signal transfer line, at least one transistor connected to the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.
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| 申请公布号 |
US6549047(B2) |
申请公布日期 |
2003.04.15 |
| 申请号 |
US20010945618 |
申请日期 |
2001.09.05 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
YAMAZAKI MASAFUMI;TOMITA HIROYOSHI |
| 分类号 |
H01L21/822;G06F1/10;G11C11/407;H01L21/82;H01L27/04;H03K5/00;H03K5/13;H03K5/135;H03L7/06;H03L7/081;H03L7/087;(IPC1-7):H03L7/06 |
主分类号 |
H01L21/822 |
| 代理机构 |
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