发明名称 Method of producing an interconnect structure for an integrated circuit
摘要 A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.
申请公布号 US6548396(B2) 申请公布日期 2003.04.15
申请号 US20010874874 申请日期 2001.06.05
申请人 APPLIED MATERIALS, INC. 发明人 NAIK MEHUL;BROYDO SAMUEL
分类号 H01L21/768;(IPC1-7):H01L21/476 主分类号 H01L21/768
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