发明名称 |
Vertical stacked gate flash memory device |
摘要 |
A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
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申请公布号 |
US6548856(B1) |
申请公布日期 |
2003.04.15 |
申请号 |
US20000583403 |
申请日期 |
2000.05.31 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LIN CHRONG-JUNG;CHEN SHUI-HUNG;LIANG MONG-SONG |
分类号 |
H01L21/8247;(IPC1-7):H01L29/788 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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