| 摘要 |
In accordance with a recent high-speed trend of the CPU, it has been demanded a semiconductor device which is capable of varying the frequency of a clock signal to be input to the CPU in accordance with the access speed of the individual peripheral devices, but without using a wait controller so as to readily cope with the case where a low-speed access peripheral device is to be accessed, and in order to meet with this demand, the semiconductor device of the present invention comprises a CPU, an address decoder that decodes an address signal transmitted from the CPU and outputs an address signal specifying signal for specifying an address area in which a designated address is included, a frequency divider that divides a base clock signal and outputs one or more than one low-speed clock signals whose frequencies have been lowered, and a clock signal decision circuit that selects as to which one of the base clock signal and the frequency-divided clock signals is to be input to the CPU in accordance with the address area specifying signal output from said address decoder.
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