| 摘要 |
An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array. The selected values from the index table and accumulation register array are combined in an adder. The value selected from the bit-reverse table is appended to the combination of the selected values from the index table and accumulation register array to form the tentative address. The tentative address generated from the first counter value is compared with a threshold value, and, based on the comparison, one of the two tentative addresses is selected as the output interleaved address. Before beginning the next iteration, the accumulated value used in generating the valid output interleaved address is updated to a new accumulated value. If not all output interleaved addresses have been generated, the counters are incremented by the same increment value, the increment value dependent upon the comparison with the threshold value, and the next iteration begins.
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