发明名称 SEMICONDUCTOR PACKAGE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor package that improves the connection reliability between chip and package electrodes, and at the same time inhibits the damage in a via in flip-chip packaging. SOLUTION: The mounting surface of a chip comprises a solder resist layer 9 and an electrode section 10. A conductor layer 7 is extended in a horizontal direction from the lower section of the electrode section 10. And the conductor layer 7 is connected to a lower internal wiring pattern 2 by a via hole 8 at the end section. There is an insulating resin layer 6 under a conductor layer 7. In this case, a layer 5 having a low modulus of elasticity is present between the internal wiring pattern 2 and insulating resin layer 6, and becomes thinner than other sections near the via hole 8 with a small diameter.
申请公布号 JP2003110062(A) 申请公布日期 2003.04.11
申请号 JP20010299776 申请日期 2001.09.28
申请人 TOPPAN PRINTING CO LTD 发明人 MANIWA SUSUMU;TSUKAMOTO TAKETO
分类号 H01L23/12;H01L23/14;(IPC1-7):H01L23/14 主分类号 H01L23/12
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