| 摘要 |
PROBLEM TO BE SOLVED: To provide a mixed delay locked loop circuit (DLL) in which variations due to influences of noises are not large, and a clock signal synchronization method therefor. SOLUTION: The mixed DLL circuit has a digital delay section 100 and an analog delay section 200. The section 100 has a digital half delay line 111 consisting of a plurality of unit delay devices, compares phases of an inputted external reference clock signal and an output clock signal generated by the mixed DLL circuit, controls a delay amount of the reference clock signal in the line 111, and locks the control on the digital half delay line if locking is performed between the reference clock signal and the output clock signal. The section 200 has an analog delay line 207, compares phases between the reference clock signal and the output clock signal, converts the comparing result into an analog signal, and then, controls the delay amount of the output signal of the line 111 in the analog delay line by using the analog signal. |
