| 摘要 |
The invention relates to a multiplexer cell (1) for converting an input signal (D0, D1) with a data input rate (fD) into an output signal (E) with a data output rate (fE) that, in particular, is twice that of the data input rate. To this end, the inventive multiplexer cell (1) comprises: a clock input connection (6) for supplying a clock signal (C0) whose frequency is equal to that of the data input rate (fD); a first and second data input connection (2, 4) for supplying a first or second input signal (D0, D1) with data input rate (fD); a data output connection (8) for outputting the output signal (E) with data output rate (fE); a first and second master-slave register circuit (22, 24), whose inputs are connected to the first or second data input connection (2, 4) and whose clock inputs are connected to the clock input connection (6), for effecting the edge-triggered output of the first or second input signal (D0, D1); a delay circuit (18), whose input is connected to the output of the second master-slave register circuit (24) and whose clock input is connected to the clock input connection (6), for effecting the delayed output of the second input signal (D1), whereby the delay is equal to a half clock period of the clock signal (C0), and; an XOR gate circuit (20) whose first input is connected to the output of the first master-slave register circuit (22), whose second input is connected to the output of the delay circuit (18) and whose output is connected to the data output connection (8). |
