Switching circuit capable of improving memory write timing and method thereof

摘要

In DRAM system where quad rate transmission is used, at least one latch is disposed within a switching circuit for increasing the data valid windows of a portion of transmitted data segments. For example, in a sequence of transmitted data segments, only the odd numbered segments are having their data valid windows increased. Thereby, the writing process of the system is improved. The system further provides at least one delay circuit for suitably matching signals for a desired result.