COMPENSATING FOR DIFFERENCES BETWEEN CLOCK SIGNALS

摘要

A clock compensation circuit 102 is provided. The circuit comprises a clock synchronization circuit 110 coupled to receive an input clock signal 101-1, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals 105. The circuit further comprises a phase comparator 120s coupled to receive one of the plurality of internal logic clock signals and a sample clock PHYRET from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel 115s coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.