发明名称 |
Clock synchronous semiconductor memory device |
摘要 |
The position information indicating the position of a memory relative to a controller is stored in a position information generating circuit, and the transfer timing of write data transmitted from an input circuit to a write circuit and the activation timing of a latch transfer instructing signal are adjusted according to this position information. Thus, the semiconductor memory device is provided that is capable of taking in and generating the internal write data reliably even when the flight time of a data bus becomes substantially the same as the cycle time of a clock signal.
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申请公布号 |
US2003067812(A1) |
申请公布日期 |
2003.04.10 |
申请号 |
US20020173263 |
申请日期 |
2002.06.18 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KAJIMOTO TAKESHI |
分类号 |
G11C11/413;G06F1/10;G06F12/00;G06F13/16;G11C7/10;G11C7/22;G11C11/34;G11C11/407;G11C11/408;G11C11/409;G11C11/417;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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