| 摘要 |
Disclosed is a scan path circuit for testing a logic circuit, which comprises a plurality of scan cells each having a scan in SI, a cell output and a clock input for receiving a clock signal, connected in series with respect to the scan ins and cell outputs. Each scan cell includes a scan flip-flop 21, and a selection circuit 31 which selects either a signal of a scan in SI or a signal of a scan out SO of the scan flip-flop 21 according on a selection controlling signal to provide the selected signal to the cell output. Determining the values of the selector controlling signal with a bypass controlling shift resister 45 permits forming a bypass between the scan data input terminal SDI and the scan in SI of any scan flip-flop except the first stage flip-flop, and/or a bypass between the scan data output terminal SDO and the scan out SO of any scan flip-flop except the final stage scan flip-flop.
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