| 摘要 |
A memory controller (1005) includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory (1015A1-1015N1). The SDRAM-interface controller configured to communicate with one or more SDRAMs (1015A2-1015N2). The SDRAM-interface controller provide a plurality of interface signals to the SDRAM via a dedicated port (5005-5025). One of the interface signals, an SDRAM address/control signal (5005), has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.
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