发明名称 COLUMN REDUNDANCY SYSTEM AND METHOD FOR EMBEDDED DRAM DEVICES WITH MULTIBANKING CAPABILITY
摘要 A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.
申请公布号 US2003067816(A1) 申请公布日期 2003.04.10
申请号 US20010971840 申请日期 2001.10.05
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ANAND DARREN L.;BARTH JOHN E.
分类号 G11C29/00;(IPC1-7):G11C7/00 主分类号 G11C29/00
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