| 摘要 |
The memory comprises a cell matrix, row decoder logic units, level conversion units (LSHx,y) and interface logic stages (ILOG) between the level conversion units and the row lines (WL) of the matrix. Each interface stage comprises elementary row driving stages, each with inputs (LXP, LYP) connected to the level conversion units (LSHx,y), an output connected to a row line (WL) and two supply terminals (SUPPLY_P, SUPPLY_N). Each elementary stage has an upper branch with a p-channel MOS transistor (P01) and a lower branch with an n-channel MOS transistor (N01). In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor (N00) in the upper branch and a p-channel transistor (P00) in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
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