| 摘要 |
A polysilicon layer including a channel region, and a source region and a drain region located on opposite sides of the channel region is formed on a lower insulating substrate. A gate wire including a plurality of gate lines and a plurality of gate electrodes, which are branched from the gate lines and overlap the channel region, and a storage wire including a plurality of storage electrodes and storage lines connected to the storage electrodes and parallel to the gate lines are formed on the gate insulating layer covering the polysilicon layer. Furthermore, a plurality of first insulating layers covering the gate wire and the storage wire are formed on the gate insulating layers. The first insulating layer has the same shape as the gate insulating layer and is formed extending to the gate wire and the storage wire. A pixel pattern including source and drain ITO electrodes made of indium tin oxide are formed on the exposed source and drain regions, and a pixel electrode connected to the drain ITO electrode is formed on the insulating substrate. Here, longitudinal edge portions of both sides of the pixel electrode overlap edge portions of storage electrodes, respectively. A second insulating layer if formed covering the source and drain ITO electrodes and the pixel electrode, and having a contact hole exposing a portion of the source ITO electrode. A plurality of data lines connected to the source ITO electrode through the contact hole and defining pixels by intersecting the gate lines is formed on the second insulating layer. The data lines are located between adjacent pixel electrodes and overlap the storage electrodes.
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