| 摘要 |
A scalable routing architecture for high density programmable logic devices involves the utilization of a two-dimensional network of non-segmented routing channels to serve as global interconnects between clusters of logic blocks. Each cluster of logic blocks is a CPLD-like structure which includes a number of logic blocks connected together by a local interconnect. Logic signals that need to enter a cluster, either from an I/O pin or from another logic block of another cluster, do so by traversing from those sources though a channel interconnect. Similarly, logic signals produced by a cluster can be routed to an I/O pin or to another logic block of another cluster across one of the channels. A switch matrix is implemented at intersections between the channels to allow logic signals to be transferred between rows and columns of the channels.
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