| 摘要 |
A clock synchronous circuit is stopped or started in accordance with the situation. More specifically, the clock synchronous circuit is stopped when no synchronous clock is necessary or in modes, such as a standby mode, bank active mode, refresh mode, and write mode, other than a read mode. In the read mode, the clock synchronous circuit is operated because a synchronous clock is necessary to output data. In the read mode, the number of clocks, i.e., CL, required from the time a read command is input to the time data is actually output, is 3 or more, when restarting and preamble of the clock synchronous circuit are taken into consideration.
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