Method and apparatus for specifying global abutment points in a semiconductor device having ambiguous submodule abutments

摘要

A method for designing a circuit having a plurality of submodules includes providing a floor plan for the circuit. The floor plan defines boundaries for each of the submodules. A component list identifying internal circuit elements of the submodules and interconnections between the internal circuit elements is provided. A plurality of global abutment points are defined for the interconnections between internal circuit elements of different submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of the boundary of a particular one of the submodules. A program storage device includes a floor plan database, a connectivity database, and program instructions. The floor plan database is adapted to store a floor plan of a circuit having a plurality of submodules. The floor plan defines boundaries for each of the submodules. The connectivity database is adapted to store information identifying internal circuit elements of the submodules and interconnections between the internal circuit elements. The program instructions, when executed by a computer, perform a method, the method comprising defining a plurality of global abutment points for interconnections between internal circuit elements of different submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of the boundary of a particular one of the submodules.