| 摘要 |
A row line selection circuit comprises first and second decoding sections and NMOS transistors. The first decoding section receives a first address signal and generates first selection signals. The second decoding section receives a second address signal and generates second selection signals. The NMOS transistors each of which has a gate for receiving one of the first selection signals, one end of a current path of each of the NMOS transistors being connected to receive the one of the second selection signals. The NMOS transistors classified into groups, each group including a predetermined number of the transistors which are prepared in correspondence with row lines lying adjacent to each other. One of the first selection signals is supplied to the predetermined number of NMOS transistors in one of the groups, and one of the second selection signals is supplied to one of the predetermined number of NMOS transistors in each group.
|
