| 摘要 |
A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port. The multiplexer is responsive to at least one path select signal and has a first input electrically coupled to the data output of the data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of the retransmit register. The data output register is responsive to a read address and has a data input electrically coupled to an output of the multiplexer and a data output electrically coupled to the data output port.
|
