发明名称 |
Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing |
摘要 |
Methods and structures for determining alignment during semiconductor wafer processing are described. In one implementation, two geometric shapes are formed at different elevations over a substrate and at least partially overlapping with one another. The two shapes are inspected for overlap to determine whether the two shapes are misaligned. If the shapes are misaligned, a magnitude of misalignment is determined from the degree of overlap of the two shapes. In another implementation, a pair of elevationally spaced-apart geometric shapes are used to translate shifts of the shapes in one direction into quantifiable shift magnitudes using another direction. In yet another implementation, shifts in both the X and Y direction are readily quantifiable through visual inspection.
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申请公布号 |
US6544859(B2) |
申请公布日期 |
2003.04.08 |
申请号 |
US20010003130 |
申请日期 |
2001.11.01 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
ZIGER DAVID;DENSION EDWARD;LEROUX PIERRE |
分类号 |
G03F7/20;H01L23/544;(IPC1-7):H01L21/76 |
主分类号 |
G03F7/20 |
代理机构 |
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地址 |
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