发明名称
摘要 An all digitally controlled self calibrating delay line method and apparatus which simulates an infinitely long delay line by continuously identifying the terminal at a physical position in said delay line (ESP) which is the exact location at which a signal traversing said delay line is phase shifted 360 degrees in relation to said phase detector input and means for connecting the said ECP terminal to the first stage of said delay line. <IMAGE>
申请公布号 JP3394307(B2) 申请公布日期 2003.04.07
申请号 JP19940004010 申请日期 1994.01.19
申请人 发明人
分类号 H03K5/14;G11C11/407;H03H11/26;H03K5/13;H03L7/081;H04L7/033 主分类号 H03K5/14
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