发明名称 DATA BUS WIRING METHOD, MEMORY SYSTEM AND MEMORY MODULE BASE BOARD
摘要 PURPOSE: To provide a data bus structure capable of eliminating unconformity of local impedance caused by additional capacity possessed by an integrated circuit such as a DRAM. CONSTITUTION: The impedance determined according to the additional capacity of a memory device is arranged in the vicinity of the memory device on a data bus.
申请公布号 KR20030027752(A) 申请公布日期 2003.04.07
申请号 KR20020058425 申请日期 2002.09.26
申请人 ELPIDA MEMORY, INC. 发明人 ABO HISASHI;IKEDA HIROAKI
分类号 G06F3/00;G06F12/00;G06F13/16;G11C5/00;G11C5/06;H01L27/10;H05K1/02;H05K1/14;(IPC1-7):H01L27/10 主分类号 G06F3/00
代理机构 代理人
主权项
地址