| 摘要 |
<p>PROBLEM TO BE SOLVED: To generate a clock signal without damaging noise immunity in a high-frequency region when this semiconductor integrated circuit is applied to a VCO in a PLL, by suppressing the change quantity of the delay in a differential voltage-controlled delay cell against the change quantity of the control voltage input to a bias circuit which supplies bias voltages to the differential voltage-controlled delay cell. SOLUTION: This semiconductor integrated circuit comprises a differential voltage-controlled delay cell 10, in which the resistance values of voltage- controlled resistor elements (VCRs) 11 are controlled by a bias voltage VCP, wherein the VCRs are connected as load resistors of a MOS differential amplifier circuit, while the current through a current-source transistor 12 is controlled by a bias voltage VCN, and a bias circuit 20 that generates bias voltages, VCP and VCN, by using a first replica circuit 21 having an equivalent constitution to that of the voltage-controlled delay cell and a second replica circuit 22 having an equivalent constitution to that of a substitute in which a VCR of the voltage-controlled delay cell is replaced with a constant resistor element 222.</p> |
