| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory in which desired operation can be performed surely and normal (setup is fulfilled) operation speed is not sacrificed even when setup for a reference clock is not fulfilled for an input such as an address or the like. SOLUTION: The device is a synchronous semiconductor memory in which a plurality of memory cells 10 are arranged in matrix, a reference signal is given to a control circuit 5, and performs read-out and write-in based on a clock generated by the control conceit 5. The device is provided with an ATD circuit 14 for detecting variation of address signals, a SAT circuit 15 for ORing a signal from this detecting circuit 14, and a circuit 16 for prohibiting internal take-in of the reference signal based on a signal from the SAT circuit 15.
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