发明名称 PROCESSOR, AND DEVICE AND METHOD FOR COMPILATION
摘要 PROBLEM TO BE SOLVED: To overcome the problem that a conditional execution instruction is executed as a non-action instruction if conditions are not met, and the use efficiency of hardware deteriorate to lower effective performance. SOLUTION: A processor decides execution conditions by decoding instructions more than mounted computing elements by an instruction issue control part 31 before an execution stage, invalidates instructions themselves whose conditions are false, and performs allocation so that the computing elements (hardware) can effectively be used for following effective instructions. A compiling device performs scheduling so that the number of instructions whose execution conditions are true does not exceed the upper limit of parallelism of the hardware. The number itself of instructions which are arranged in parallel in each cycle may exceed the parallelism of the hardware.
申请公布号 JP2003099248(A) 申请公布日期 2003.04.04
申请号 JP20010286393 申请日期 2001.09.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HEIJI TAKEHITO;TAKAYAMA SHUICHI;TANAKA TETSUYA;OGAWA HAJIME;HIGAKI NOBUO
分类号 G06F9/30;G06F9/318;G06F9/38;G06F9/45 主分类号 G06F9/30
代理机构 代理人
主权项
地址