WAFER BURN-IN MODE CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a wafer burn-in mode circuit for performing efficiently screening operation of a memory cell in a DRAM. SOLUTION: A wafer burn-in mode circuit 10 for performing screening of a memory cell is provided with a terminal (STRESS terminal) 19 for applying the stress. Normal decoders are constituted so as to be made to all word lines selection at the time of applying the stress, while a potential of a bit line is set to 0 V to enlarge voltage VGS between a gate and a source of a memory cell transistor MC.