MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To generate an appropriate sense amplifier activating timing signal by a dummy cell and to prolong a wiring lifetime of a dummy word line and a dummy bit line. SOLUTION: This device is provided with two groups of dummy cell columns having respectively fixed dummy cells 21A, 21B and dummy bit lines 13A, 13B, two groups of dummy word lines 12A, 12B accessing respectively each fixed dummy cell 21A, 21B of each dummy cell column, and a dummy cell control circuit 9 selecting dummy word line 12A, 12B. A timing circuit 5A generates a timing signal ts with timing based respectively on dummy bit line signals BA, BB propagated to each dummy bit line 13A, 13B of each dummy cell column. The dummy word lines 12A, 12B, two pairs of dummy bit lines 13A, 14A and dummy bit lines 13B, 14B are operated successively for each cycle of a clock.