发明名称 |
High speed sampling receiver with reduced output impedance |
摘要 |
A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.
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申请公布号 |
US2003062939(A1) |
申请公布日期 |
2003.04.03 |
申请号 |
US20020232657 |
申请日期 |
2002.09.03 |
申请人 |
NEC CORPORATION |
发明人 |
TANAKA KENICHI;MINAMI KOUICHIROU |
分类号 |
H03K17/00;H03K3/012;H03K3/0233;H03K3/356;H03K3/3562;H03K19/0185;(IPC1-7):H03K3/289 |
主分类号 |
H03K17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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