| 发明名称 |
Method and apparatus for increasing load bandwidth |
| 摘要 |
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.
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| 申请公布号 |
US2003065908(A1) |
申请公布日期 |
2003.04.03 |
| 申请号 |
US20010968474 |
申请日期 |
2001.09.28 |
| 申请人 |
PATEL RAJESH;DUNDAS JAMES;YOAZ ADI |
发明人 |
PATEL RAJESH;DUNDAS JAMES;YOAZ ADI |
| 分类号 |
G06F9/30;G06F9/38;(IPC1-7):G06F9/30 |
主分类号 |
G06F9/30 |
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