发明名称 Failure propagation path estimate system
摘要 The present invention provides a technique relating to a failure propagation path estimate system which can realize an estimate process by adding the measurement result to the failure location estimate results estimated prior to the measurement, and which can realize high-speed re-calculation of only part of a large-scale circuit relating to the measurement point. As shown in FIG. 1, the failure propagation path estimate system according to the present embodiment is generally provided with an input device 1 such as a keyboard or an interface for external devices, a failure propagation path estimate processor (failure propagation path estimate device, error propagation path estimate processor) 2 operated under the control of a program, a storage device 4 for storing information necessary for the failure propagation path estimate process, and an output device 5 such as a display device, a printer or an interface for external devices.
申请公布号 US2003066000(A1) 申请公布日期 2003.04.03
申请号 US20020194773 申请日期 2002.07.12
申请人 NEC CORPORATION 发明人 SHIGETA KAZUKI
分类号 G01R31/317;G01R31/08;G01R31/28;G06F11/25;(IPC1-7):G01R31/28 主分类号 G01R31/317
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