| 摘要 |
A method and architecture with which to achieve efficient sub-word parallelism for multiplication resources is presented. In a preferred embodiment, a dual two's complement multiplier is presented, such that an n bit operand B can be split, and each portion of the operand B multiplied with another operand A in parallel. The intermediate products are combined in an adder with a compensation vector to correct any false negative sign on the two's complement sub-product from the multiplier handling the least significant, or lower, p bits of the split operand B, or B[p-1:0], where p=n/2. The compensation vector C is derived from the A and B operands using a simple circuit. The technique is easily extendible to 3 or more parallel multipliers, over which an n bit operand D can be split and multiplied with operand A in parallel. The compensation vector C' is similarly derived from the D and A operands in an analogous manner to the dual two's complement multiplier embodiment.
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