| 摘要 |
PROBLEM TO BE SOLVED: To provide a BIST circuit, capable of easily satisfying timing restrictions in inspection in a semiconductor circuit, to thereby easily cope with high speed operation, and easily reducing the man-hour for logic synthesis and layout. SOLUTION: A D-flip flop 8 is automatically inserted between the final stage register of a pattern generator 4 and a branch point 7. Logical stage numbers of a path from the final stage register of the pattern generator 4 to the first stage register of an inspection object circuit and a path from the final stage register of the pattern generator 4 to the first stage register of a comparator 6 and the physical wiring length between the registers are divided at the branch point 7.
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