Generating non-integer clock division

摘要

A clock divider and method is disclosed for generating an output clock signal having a frequency that is a fractional or integral multiple of a reference clock signal frequency. In one embodiment, the clock divider divides a clock signal by a first divisor in a first period and by a second divisor in a second period, where the second period following the first period. The clock divider circuit is triggered by a first edge of the clock signal and generates a first signal. A synchronizing circuit is coupled to the clock divider to generate a second signal from the first signal, the second signal being synchronized by a second edge of the clock signal, where the second edge is in a direction opposite to the first edge. A selector is coupled to the synchronizing circuit and the clock divider to generate an output signal by selecting the first signal and the second signal alternately between the first period and the second period.