| 摘要 |
The invention relates to a circuit arrangement for generating non-overlapping clock phases. Said arrangement comprises a first switchgear unit (SE1) for linking two input signals to an output signal and a second switchgear unit (SE2) for linking two input signals to an output signal, whereby a respective first input (E1.1, E2.1) of the first and second switchgear units (SE1, SE2) is provided for the application of a common clock signal (clk). In addition, the arrangement is provided with a first multiplexer unit (ME1). According to the invention, a first input (E3.1) of said multiplexer unit is connected to an output (A1.1) of the first switchgear unit (SE1), a second input (E3.2) is connected to an output (A2.1) of the second switchgear unit (SE2), the output (A3.1) of the multiplexer unit is connected respectively to a second input (E1.2, E2.2) of the first and second switchgear units (SE1, SE2) and a third input (E3.3), which switches between the inputs of the first multiplexer unit (ME1) and to which the clock signal is applied, is provided. Several non-overlapping clock phases are supplied by output signals of the first and second switchgear unit (SE1, SE2) and also of the first multiplexer unit (ME1). |
