Test circuit for semiconductor memory and semiconductor memory device

摘要

According to the present invention, a pseudo-error signal generating circuit is provided between a memory circuit and a self-test circuit. The pseudo-error signal generating circuit converts an output signal of the memory circuit based on a setting signal to supply a pseudo-error signal necessary to verify the operation of the self-test circuit. The pseudo-error signal generating circuit has a scan chain circuit in which a setting signal is set, and generates a pseudo-error signal based on the setting signal.