Semiconductor memory device including clock-independent sense amplifier

摘要

A semiconductor memory device includes a memory cell array (ARRAY), a read control circuit (CNTROL1), a row decoder (ROWDEC), a column decoder (COLDEC), a sense amplifier (S/A), and a sense amplifier control circuit (SENGEN). The read control circuit (CNTROL1) produces a precharge signal (PRCV) to precharge a bit line (BL) of the memory cell array (ARRAY). The sense amplifier (S/A) amplifies data read onto the bit line (BL). In reading data from a memory cell (MC), the sense amplifier control circuit (SENGEN) enables the sense amplifier (S/A) and inhibits entry of read data from a memory cell (MC) into the sense amplifier (S/A) only for a fixed interval after a fixed time after the precharging signal (PRCV) has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier (S/A) while the sense amplifier (S/A) is being disabled.