发明名称 Delay estimation for restructuring the technology independent circuit
摘要 Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
申请公布号 US6543037(B1) 申请公布日期 2003.04.01
申请号 US19990465498 申请日期 1999.12.16
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 LIMQUECO JOHNSON CHAN;LI HONG;BELKHALE KRISHNA;VARMA DEVADAS
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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